1. Field of the Invention
The invention relates to semiconductor memory devices and, more particularly, to a method for patterning dielectric layers on semiconductor substrates to produce contact holes or trenches in the dielectric layer.
2. Background Information
To continue increasing the power of microprocessors and memory chips, it is necessary for the dimensions of the individual microelectronic components, such as capacitors or transistors, to be constantly reduced further. This allows a higher integration density to be achieved on a given chip surface area and also allows the operations carried out per unit time to be shortened. To enable the integration density to be further increased, different microelectronic components are increasingly being stacked on top of one another in layers. To allow the individual microelectronic components in each case to be driven in a controlled manner, therefore, it is necessary to use a plurality of interconnect levels that are arranged above one another and are in each case isolated from one another by insulating dielectric layers.
During production of a microchip, the structures of the individual components are generally produced by sequential deposition of layers of different materials. To allow targeted processing of sections of these layers, masks are produced from a photosensitive resist that can be patterned using lithography methods. After the exposed photoresist has been developed, during which step certain sections of a layer of the photoresist are removed selectively, sections of the layer arranged beneath the resist mask are uncovered and can then be processed selectively. After the processing step, the resist mask is removed again. For this purpose, the resist mask can, for example, be dissolved using a suitable solvent or incinerated in an oxygen plasma. This is generally followed by a wet-chemical cleaning step in order to remove residues of organic materials and oxide layers that were formed in the oxygen plasma from the surface.
During the production of a contact hole, through which a conductive connection is to be produced between an electronic component arranged in a lower level, such as the source contact of a transistor, and an interconnect arranged in a higher level, the procedure has hitherto been, in the most simple case, for an insulating dielectric layer to be deposited on the level which comprises the contact of an electronic component and to which a conductive connection is to be produced. A layer of a photosensitive resist is deposited on this dielectric layer, and the resist layer is then exposed in sections and developed in a conventional manner such that the dielectric layer is uncovered in the section in which the contact hole is to be introduced. Then, the contact hole is etched into the dielectric layer using a suitable plasma, for example, a fluorine-containing plasma, so that the contact to the microelectronic component is uncovered at the base of the contact hole.
Next, the resist film or resist mask is incinerated in an oxygen plasma. The incineration is carried out at a temperature of approximately 250° C. within approximately 1 to 1.5 minutes. The oxygen plasma is generated from a gas mixture which substantially comprises oxygen and to which small quantities of a forming gas have been added. The forming gas serves to stabilize the plasma and usually consists of a mixture of nitrogen gas and hydrogen gas. The proportion of the forming gas in the gas for generating the oxygen plasma is generally selected to be between 3 and 10% by volume, usually in the region of approx. 5% by volume. This is followed by wet-chemical cleaning of the patterned surface of the dielectric layer under oxidizing conditions in order to remove organic residues adhering to the surface. An example of a standard cleaning agent is H2SO4 in combination with O3.
The contact that is uncovered at the base of the contact hole usually consists of silicon which is provided, for example, with a doping. Therefore, a thin film of oxide is formed in the oxygen plasma or as a result of oxygen or water from the ambient air, and this thin film of oxide must first be removed before the contact hole is filled with a conductive material. For this purpose, the surface is cleaned using highly dilute aqueous hydrofluoric acid which is buffered, for example, with NH4F. However, this removes not only the oxide layer at the base of the contact hole, but also material on the side walls of the contact hole. Therefore, the cleaning with buffered hydrofluoric acid widens the structures which have been etched into the dielectric layer. The same problem arises if the contact is composed of a metallic layer, for example for producing Vias between interconnect levels arranged above one another. In this case too, an oxide layer is formed on the surface of the contact and must firstly be removed before the contact hole is filled. Hydrofluoric acid can be used as a standard etchant for this purpose.
With the current feature sizes that are realized in the production of microchips, it is possible to control the widening by optimizing the process conditions for cleaning with dilute hydrofluoric acid. For this purpose, by way of example, the concentration of the hydrofluoric acid, the temperature at which the cleaning is carried out and the duration of the cleaning can be optimized. Furthermore, when designing the chip it is possible to take into account the widening of the contact holes or trenches that occurs during the cleaning using dilute hydrofluoric acid. The widening that has to be taken into account as a result of the cleaning using buffered dilute hydrofluoric acid is currently in the range from approx. 25 to 38% with respect to the etched dimension. A further reduction in the widening by, for example, shortening the cleaning time no longer appears possible, since in this case the oxide layer on the contact at the base of the contact hole can no longer be removed to a sufficient extent.
Future chip technology will require the production of a critical feature size in the region of 90 nm or below. In this case, it is no longer possible to take account of the widening of the contact holes which are introduced into a dielectric layer when designing the microchip. Since the widening of the contact holes is independent of the diameter thereof, i.e. becomes ever more pronounced as the feature size is reduced, it is imperative to find ways of producing contact holes with the required high level of accuracy even for a critical feature size of less than 90 nm.